The present disclosure relates to systems and methods for providing gate signals to rows of pixels in an electronic display device.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
As screen sizes, resolutions, and refresh rates for electronic displays increase, providing gate signals to each row of pixels of an electronic display may prove to be more challenging. That is, when providing a gate signal for a respective row of pixels, a gate driver circuit may have a limited amount of time to receive a clock signal used to output a respective gate signal. To ensure that the gate driver circuit is prepared to receive the rise and fall times of various clock signals for outputting respective gate signals for respective rows of pixels, the gate driver circuit may overlap gate enable signals (e.g., clock signals) used to output gate signals for the different rows of pixels. During a portion of this overlapped period, the gate driver circuit may pre-charge a gate of a respective switching circuit, such that the respective switching circuit is active prior to when a respective clock signal used to output the gate signal is received. By overlapping gate enable signals, the gate driver circuit may enable the display to depict image data for displays having larger screen sizes, higher resolutions, and faster refresh rates, as discuss above. However, to minimize the number of circuit components employed by the gate driver circuit to provide these overlapped enable gate signals (e.g., clock signals), improved systems and methods for operating a gate driver circuit are desirable.